[HARDWARE] bit serial adders

stoney at sequent.com stoney at sequent.com
Mon Oct 4 11:36:05 EDT 1999

What do you think about using bit serial adders for a 
reprogrammable FPGA solution.  Since through put is 
more important for this application than latency you
might be able to get higher throughput by using 
bit serial adders.

  through put = #engines * keyrate/engine 

The wide programmable rotates and adds are difficult to
implement in Alter flex 10k or Xilinx XC4000 fpga's.  There
is dedicated carry logic in both devices.  Xilinx claims
that the dedicated carry logic makes carry look ahead adder
using the generate, propagate logic a marginal benefit for
32 bit adds.

There is a paper by Ian Goldberg and David Wagner, 
"Architectural Considerations for Cryptanalytic Hardware".


They implemented several algorithms using Altera flex 8k
devices which also has the dedicated carry logic, but no
large LUTs 

  (Look up table, SRAM, the address is the input to a boolean
   function and the contents of that memory location is the

called EABs in the 10k devices.  They found that
RC4 is better implemented in software than accelerated by
the flex 8k devices due to the ADDs.

A friend recommended the bit serial adder approach.  He used
it for FFTs



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