[HARDWARE] Just Courious......
jakari at fribble.cie.rpi.edu
Mon Oct 11 01:16:21 EDT 1999
On Mon, 11 Oct 1999, Jerome Lamarque wrote:
> >Thing is, ROL just isn't used that much, so cpus like the DEC Alpha, IBM
I wrote this, let me justify that as: isn't used that much in
things other than RC5... one less thing to make the instruction decoder
> I can assure you *every* PowerPC *has* the ROL instruction built in.
> All PowerPC processors are RISC based processors and are faster at
RISC, but still a pretty huge instruction set overall. I figured
that it had ROL, but without a ref. book at hand, I wasn't entirely sure.
> "rotate-left" instruction which is used massively by rc5. The
> processor has to emulate the instruction which takes a lot of cycles
> (up to 8).
And if you're curious, this works out to about 1200 CPU cycles per
key on an Alpha 21066 (EV4). About 500 cycles/key on Pentium MMX.
As a guy with a number of Alpha servers, it makes me wish for more DES
contests. Then I'm not handicapped by lack of ROL.
> POWER architecture, therefore I *think* POWER processors have it
I have that book somewhere, so I'll check. Unfortunately, my
IBM RS6k's (with POWER cpus) are old- like 40MHz clocks- so perfomance is
poor anyway (~37kkey/sec on my 530). But it is roughly twice as fast as
my 40MHz SPARCs, so you're probably right that they do ROL, and I didn't
think too deeply before when I said they didn't. My bad.
My view is that the POWER/P2SC/P3 cpus are really optimized to
have high I/O throughput, not phenomenal number-crunching power, so they
never look real good in these contests (or SPECint/fp, for that matter.)
The IBM's also about ten times as large, ten times the weight, ten
times the power usage, and is generally ugly looking, so the Sun has
something going for it ;)
Insert witty comment here
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