[HARDWARE] Just Courious......
jakari at fribble.cie.rpi.edu
Wed Sep 15 20:10:15 EDT 1999
On Wed, 15 Sep 1999, Marcus Gillette wrote:
> Actually, as I understood it, from the rc5 FAQ, RISC architecture isn't as
> good at working on rc5. The reason is becuase CISC processors have the
> instruction set the rc5 client uses, whereas the RISC processor would have
> to emulate that instruction set. I don't know, but maybe I'm wrong.
Yes, in a way.
The _architecture_ doesn't matter- but RISC means *reduced*
instruction set. Which means that to speed up the most common
instructions, you get rid of the least common ones. The x86 CISC has the
rotate-left instruction built in, as well as some variants of rotate.
Thing is, ROL just isn't used that much, so cpus like the DEC Alpha, IBM
POWER/P2SC, MIPS and maybe some others leave it out. So the compiler has
to fake ROL by shift-left and some tricks.
I *think* PowerPC has ROL built in or at least a fairly quick
"macro" implementation, so it compares better to x86 for RC5.
What I need are more DES contests so I can show off all the Alpha
muscle we've got around here ;)
Insert witty comment here
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