[HARDWARE] Just Courious......
jakari at fribble.cie.rpi.edu
Wed Sep 15 23:44:21 EDT 1999
On Wed, 15 Sep 1999, Robert Norton wrote:
> Martin Harvey wrote:
> > What about using an FPGA? Perhaps some sort of Xilinx thingy? They're
> > fairly cheap :-)
> I think one of the larger Altera or Xilinx devices should hold the algorithm just
50K gates? I'd hope the code would fit.
> boards for under $100 even in small quantity, I think. I thought about doing it,
> but I'm not familiar with schematic capture for FPGA's, and I don't have any
That's easy. It's the actual logical design that takes time.
I've got access to the boards, the chips, and the tools, but unfortunately
not the time to build RC5 crackers. Fun to talk about though.
Single FPGA cards for $100 seems reasonable. However, FPGAs are
relatively expensive- like $50 a piece or more for the bigger parts.
You could do it in several cheaper parts, and then pipeline the heck out
of it. Maybe only 25MHz, but if cranks through a key every 5 cycles or
At any rate (no pun intended) I'm glad to see the hardware list
having some discussion again.
Insert witty comment here
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