[HARDWARE] Just Courious......

Robert Norton rjn at execpc.com
Wed Sep 15 23:57:07 EDT 1999


Jameel Akari wrote:

> On Wed, 15 Sep 1999, Robert Norton wrote:
>
> > Martin Harvey wrote:
> > > What about using an FPGA? Perhaps some sort of Xilinx thingy? They're
> > > fairly cheap :-)
> >
> > I think one of the larger Altera or Xilinx devices should hold the algorithm just
>
>         50K gates?  I'd hope the code would fit.

It takes a couple of gates to make a latch (depending on what in a cell, I guess) and
you need a stack of latches to make the entire decryption process.  Fully unrolled,
that is to say fully pipelined, I think it would still fit, but there wouldn't be 90%
left over.

> > boards for under $100 even in small quantity, I think.  I thought about doing it,
> > but I'm not familiar with schematic capture for FPGA's, and I don't have any
> > tools.
>
>         That's easy.  It's the actual logical design that takes time.
> I've got access to the boards, the chips, and the tools, but unfortunately
> not the time to build RC5 crackers.  Fun to talk about though.

Some schematics were available, maybe I can dig up the links if nobody has them handy.
They weren't fully pipelined, though.

>         Single FPGA cards for $100 seems reasonable.  However, FPGAs are
> relatively expensive- like $50 a piece or more for the bigger parts.
> You could do it in several cheaper parts, and then pipeline the heck out
> of it.  Maybe only 25MHz, but if cranks through a key every 5 cycles or
> so..

Yup, I was planning on 1/2 the cost going right into the FPGA, maybe $10 for the box
and connector, $20 for board and support chips, and maybe $20 for profit.  $$$  Sell a
thousand of those babies for $100 each (and I *will* buy one) and get yourself a new
car free. (as long as you don't declare the earnings!  :-> )
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