[HARDWARE] Just Courious......

William Scott Lockwood III scottlockwood at hotmail.com
Thu Sep 16 07:38:56 EDT 1999


Try to get it build in some fassion that chips can be added later, I.E. have
like 8 or 16 sockets on the board, with 2 proc's being the default.  I'll take
one for sure...

Scott

----- Original Message -----
From: William J [on the road] Halverson <william at netpros.net>
To: <hardware at lists.distributed.net>
Sent: Thursday, September 16, 1999 6:30 AM
Subject: Re: [HARDWARE] Just Courious......


| I forwared this on to a guy in Campbell CA who does this for a living ... he
certainly
| could do the
| entire design/program job himself ... he'd probably want someidea how many
of these
| things people
| would want in an initial run.
|
| Besides the DES etc projects ... what about the new SETI program?  Would
this approach
| [dedicated FPGA]
| be interesting to folks involved with SETI?
|
|
|
|
| Robert Norton wrote:
|
| > Martin Harvey wrote:
| >
| > > Jesper Monsted wrote:
| > > >
| > > > I think you'd get a lot more performance/price with a special RISC
chip or
| > > > with a small celeron. Anything 32-bit would do, though (i tried coding
it
| > > > for an Atmel 8-bit microcontroller, but it was dreadfully slow).
| > >
| > > What about using an FPGA? Perhaps some sort of Xilinx thingy? They're
| > > fairly cheap :-)
| >
| > I think one of the larger Altera or Xilinx devices should hold the
algorithm just
| > fine, along with a "next code" generator and a detect flag comparitor, so
you'd
| > just put in a block seed code, and finally get a go/no-go for the block
out. I
| > think you could build it onto a small plastic USB box, it can get its
power from
| > the cable.  The USB interface chips are only a buck, it would be much
cheaper than
| > a PCI card with the PCI interface chips.  No NRE costs for FPGA's, if
somebody
| > invested the time (considerable) making the circuit, you could replicate
the
| > boards for under $100 even in small quantity, I think.  I thought about
doing it,
| > but I'm not familiar with schematic capture for FPGA's, and I don't have
any
| > tools.
|
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