[HARDWARE] Just Courious......

Dan Oetting oetting at gldmutt.cr.usgs.gov
Thu Sep 16 10:59:30 EDT 1999

At 22:44 -0400 9/15/1999, Jameel Akari wrote:
>On Wed, 15 Sep 1999, Robert Norton wrote:
>> Martin Harvey wrote:
>> > What about using an FPGA? Perhaps some sort of Xilinx thingy? They're
>> > fairly cheap :-)
>> I think one of the larger Altera or Xilinx devices should hold the
>>algorithm just
>	50K gates?  I'd hope the code would fit.

Have any of you tried doing the math?

The RC5 algorithm is mostly rotates and adds. The rotate can be broken down
into a series of selectors. A 4 to 1 selector takes 5 gates per bit, A 2 to
1 selector takes 3 gates. A 32 bit dynamic rotate built with 2 x 1:4 and 1
x 2:1 selectors requires 416 gates. An adder takes about 10 gates per bit
(more if you want fast carry) or 320+ gates for a 32 bit add. Each
iteration of RC5 contains 4 adds, 1 dynamic rotate and 1 fixed rotate
bringing the total to 1696 gates per iteration (the fixed rotate is free!)
There are 26 iterations in each of 3 rounds (we're over 132k gates now).
The last round adds a rotate, xor and add for the actual encryption
(another 21k gates).
If you wanted to pipeline the process you need to latch the intermediate
results that carry between the stages. In RC5 there are 29 x 32bit
registers that need to be latched between stages needing another 2k gates
per stage.

Assuming you could get a FPGA with 250k+ gates we haven't begun to discuss
layout. These gate arrays don't allow random point to point connections.
They are constrained by the interconnect grid.

Dan Oetting <dan_oetting at comug.com>

PowerPC 603/604/750 -- Still the fastest RC5 core on the net
(but not for long...)

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