[HARDWARE] Just Courious......

ENOJON at delphi.com ENOJON at delphi.com
Fri Sep 17 10:53:03 EDT 1999


<<> > I think you'd get a lot more performance/price with a special RISC chip or
> > with a small celeron. Anything 32-bit would do, though (i tried coding it
> > for an Atmel 8-bit microcontroller, but it was dreadfully slow).
>
> Actually, as I understood it, from the rc5 FAQ, RISC architecture isn't as
> good at working on rc5.  The reason is becuase CISC processors have the
> instruction set the rc5 client uses, whereas the RISC processor would have
> to emulate that instruction set.  I don't know, but maybe I'm wrong.

It all depends on the CPU - The instruction missing from most RISCs is the
Rotate Left/Right. If you can find a CPU with those instructions embedded,
they'd probably be faster than the x86 family.

I'm pretty sure the StrongARM has ROTL/ROTR...
>>
 
It also depends on the rc5 algorithm.  Some algorithms are simply using
integer arithmetic vs. rotations--especially true of some x86 algorithms.
mj
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