[HARDWARE] Cracking engine wish list

Stelios Koroneos skoron at netor.gr
Sat Sep 18 15:05:26 EDT 1999


Based on the e-mails i received and the replies to the list a cracking engine should have
the following for people to use it

Price-Performance ratio  = <100$/1Mkeys
Serial interface (Easy to hook to existing platforms)
Expandability (Connect more devices in parallel or in a chain)
Small form factor (size)

The ability for the device to be re-programmed by the end user is not so high on the wish
This can be because at this price range more people are willing to "boost" their cracking
performance with little or no work (Plug and Crack :-)
A big network of "custom" cracking engines does not look so appealing, possibly because
Quake and letters to granny are not fisable at this point :-)

It seems that the only possible sollution would be an mcu+fpga hybrid system.
The mcu would handle protocol/communiaction issues with the client soft and even do
pre-processing for the fpga (create the key table maybe). This way the fpga can have a
lower gate count and cost.

In order to get support from d.net a working prototype must be presented first.
To do this we need the following
1. Protocol definition
We need to define what will be the sequence of communication between the host client soft
and the cracking engine(s). I think someone from d.net would be more appropriate to have
a first look at this and propose a possible protocol. D.net allready has experience in
designing the comms with remote hosts.

2. Decide which part of the rc5 code should be in the fpga and what part in the mcu
This would clarify the design goals and specs  both for the mcu and the fpga
People who have coded clients/implementations (in soft or hardware) of the RC5 can help
in this stage to decide which part of the code need to be implemented in which part.

3. Design the mcu and fpga "programs"
As far as i know there are several "public" fpga cores for a number of encryption
standards. Contacting the authors and requesting their help migh be the most appropriate
as it will save time and costs.

4. Implementing a working prototype and checking it...

Well it sounds easy on "paper" (or bytes more appropriate) but are there any people who
are willing to put their code/efforts to do domething like this ?
I can help with the mcu part, but more people are need it if we want to do something in a
relative short time (3-6 months)

One last note.
This is not an effort to make money. Design details should be made availiable for free,
so if someone wants to make the cracking engine on their own can do it.
As d.net wants to be sure that the results comming out from this design are correct,
maybe it will be necessary not to publish the fpga code or the mcu code and provide
programmed mcu/fpga at cost  to people who want to make their own engine.
After the end of the competition all code can be released to the public.



mRgOBLIN wrote:

> Jesper Monsted wrote:
> > [snip]
> > > Now regarding to cost, cracking speeds etc...
> > >
> > > When Jasper Monstead said he implemented the RC5 on the AVR i asked him for more
> > > info and told me that his code was doing approx 10kkeys. Assuming that he was
> > > using a 12 mhz AVR, this on 64 card would translate to 640kkeys.
> > > Cost of the card (hardware only)
> > > 64 pcs  90s2343 x 1,5$                           =  96
> > > 64 pcs 12 Mhz resonators x 0,5$             =  32
> > > 1 pc    90s8515 x  5$                               =    5
> > > 1 prototype board designed inhouse   30$ =  30
> > >
> > >                               Total                              163$
> > >
> > > Development cost  0 (It was a interesting project to do :-)
> > >
> > > Well does it worth it ? You have to tell me that as i don't have a clue what a
> > > good key rate should be...
> > > One last note.
> > > If instead of the AVR we use the SCENIX mcu at 50Mhz (there is 100Mhz variant
> > > also) since this is also a RISC with most instructions single cycle, the
> > > price/performace ratio will be a bit better for the 50Mhz (50Mhz SCENIX approx 5$
> > > per pcs at 100 pcs order) and much much better at 100Mhz... Any takers ?
> > >
> > > Please understand that the above are ideas and hands on implementation of some of
> > > the ideas so a final workign system might require modifications...
> > >
> > > Ideas, congratulations :-) and critisism :-( are welcome
> >
> > Well, congratulations on actually having a concept done (when the rest of
> > us are just blowing hot air :))
> >
> > Unfortunately, the keyrate/price is not quite as good as it would be,
> > using regular PC parts, networked together :(
> >
> > [all danish prices]
> > Abit BH6 main board     $110
> > Celeron 433 (->600?)    $110
> > Crappo network card     $20
> > Floppy drive            $20
> > Total:                  $260
> >
> > Roughly twice the price, but triple the performance at approx.
> > 1.6mkeys, and could probably be improved greatly by using a BP6
> > mainboard and dual celerons...
> >
> > Cool idea, i just think the crack engines need to be spiffed up a bit -
> > maybe your infrastructure and a FPGA or other crack engine?
> >
> > /Jesper
> >
> > "Microsoft does have a Year 2000 problem. We're it"
> > (c) unknown       - Go Linux! http://www.linux.org/
> >
> >  Jesper Monsted - RIPE: JM42 - jesper at monsted.com
> >
> > --
> > To unsubscribe, send 'unsubscribe hardware' to majordomo at lists.distributed.net
> Yeah I just put together a system.
> I'll try to roughly convert to $US
> ABIT BP6  $150.00
> 2x 366a Celerons $150.00 for the pair
> overclocking them at 523Mhz
> Running  <plug> SLACKWARE LINUX </plug>
> and getting 2.93Mkeys and one helluva  big smile :)
> And for my money .....I can play Quake or write a letter to Granny with it  :)
> As I see it ...... also take into consideration the advances in CPU Mhz and
> architechture are reducing  the cost per kkey/sec at quite a fast rate .
> So whatever this piece of hardware can do would have to be pretty impressive.......
> BTW anyone have any keyrates from an Athlon yet ?
> --
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