[HARDWARE] Just Courious......]]

taniwha taniwha at taniwha.com
Sun Sep 19 08:14:49 EDT 1999


On Sat, 18 Sep 1999, Robert Norton wrote:
 
> Thanks for the info, I didn't understand that the rotate was data dependent!  So it will
> take more gates to fully unroll the algorithm, dang it.  Might it still fit into a $50
> Xilinx part?  For me, the idea of 25Mkey/sec in a small, (cheap!,) box is very exciting.

it's more than that - it takes 3x26 turns through the datapath (ie 3x26
clocks) - with storage 
for 26 32-bit sets of intermediate values - I think you can fit it in a sub
$50 FPGA
(just) but I'd doubt you can get it to run at over 50MHz for 50/(3*26) =
~640Kk/sec

you aren't going to get really high key rates without either lots of
silicon or
lots of clocks 

I also looked at S/A DSPs (I think the sharc had a 32-bit rotate and enough
internal
storage to load code and data from outside and set it running without any
other
external chips) something like that may be a better solution for that cheap
cracker-box

	Paul Campbell
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