[HARDWARE] Just Courious......]]

Robert Norton rjn at execpc.com
Sun Sep 19 15:48:10 EDT 1999


taniwha wrote:

> it's more than that - it takes 3x26 turns through the datapath (ie 3x26
> clocks) - with storage
> for 26 32-bit sets of intermediate values - I think you can fit it in a sub
> $50 FPGA
> (just) but I'd doubt you can get it to run at over 50MHz for 50/(3*26) =
> ~640Kk/sec
>
> you aren't going to get really high key rates without either lots of
> silicon or lots of clocks

Maybe I'm not understanding this right, but if the algorithm is fully unrolled, that is to say
fully pipelined, wouldn't you get one answer out with each clock? So even a lowely 25Mhz FPGA
would be cranking out 25MKeys/sec.   Even if two $50 parts were needed, that would make a $150
box that did 25Mkeys/sec, or $6/Mkey/sec, still a great deal!


--
To unsubscribe, send 'unsubscribe hardware' to majordomo at lists.distributed.net



More information about the Hardware mailing list