[HARDWARE] Just Courious......]]
rjn at execpc.com
Sun Sep 19 17:57:23 EDT 1999
> As I said above I think you need either a lot of clocks or a lot of
> silicon (your design would be at the 'lot of silicon' end of the
> spectrum - and would probably take roughly the same area as
> 25 1Mkey/sec engines laid down side-by-side - it probably won't
> fit on a $100 FPGA.
I'm quite disappointed. I understand that there are 78 "steps" now, and that each step needs a
latch, and a barrel shifter, some adders and a mux, all 32 bits wide. So that might be 78*32* N
gates, where N is a relatively small number (10?) Is it the feeding forward that makes this N**2
instead of linear with steps? Thanks, Bob Norton.
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