[HARDWARE] Just Curious......]]
rjn at execpc.com
Sun Sep 19 22:18:37 EDT 1999
> >I'm quite disappointed. I understand that there are 78 "steps" now, and that each step needs a
> >latch, and a barrel shifter, some adders and a mux, all 32 bits wide. So that might be 78*32* N
> >gates, where N is a relatively small number (10?) Is it the feeding forward that makes this N**2
> >instead of linear with steps? Thanks, Bob Norton.
> sadly N is much larger than 10 - a 'gate' as usually quoted is a
> basic 2-input nand gate (ie 4 transistors) - a hold flop (with
> scan) comes out at 9-10 'gates', a D flop maybe 6-8 'gates',
> a latch is ~3 'gates', hand laid out structures like srams
> are going to be a bit smaller.
> Consider a pipe stage consisting just of a barrell shifter (doing rotate)
> (forget the mutiple 32-bit adders for the moment) - each bit of such
> a structure is basicly a 32:1 mux - a quick estimate of size for
> this is ~40 gates - so each bit of the pipe is going to be 6 (D flop)
> plus 40 (mux) - 46 'gates'.
> In reality things are much more complex - it's probably about a year
> since I immersed myself in this problem but from memory primitives
> you need to build this with are 2 barrel shifters, 6 32-bit adders,
> a 32-bit xor, some misc logic, a and about 700 bits of temp storage
> (I think that some of the adders could be reused between phases - or
> with more storage you could have more keys in flight through the
> pipe - maybe 3 sets).
> The design I did (again see my web page) is further piped to bring
> up the clock rate - I did this primarily for FPGA implementation
> because in a lot of modern FPGAs flops and sram arrays are pretty
> cheap while random logic (and routing for it) is slow. I don't have
> much recent experience with FPGAs - they seem sooo slow compared with
> the silicon I usually design with where clocks in the 200-500MHz
> range are common and gates are cheap but wiring is expensive (at
> least these days it is). In the end I didn't get past putting the
> design into Xylinx's cheapo cad program - mistly because I couldn't
> figure out how to turn my design into an OS source hardware project
> that real people could build (again - this was the 'how will ordinary
> mortals actually solder these @#$!* SMT things' problem).
More great info, thanks! I think the prototyping would have to be done as a short run at a surface
mount house. FPGA design would have to be validated in simulation, wouldn't it? Would it be too big
to simulate? Maybe money for development could be raised by pre-selling some boxes once a reasonably
accurate price is known. I think people who pre-buy get them should pay a slightly lower cost than
those buying off the shelf, in recognition of the risk being taken.
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