[HARDWARE] Just Courious......]]

Dennis Lubert plasmahh at dialup.nacamar.de
Mon Sep 20 18:12:34 EDT 1999


At 14:48 19.09.99 -0500, you wrote:
>taniwha wrote:
>
>> it's more than that - it takes 3x26 turns through the datapath (ie 3x26
>> clocks) - with storage
>> for 26 32-bit sets of intermediate values - I think you can fit it in a sub
>> $50 FPGA
>> (just) but I'd doubt you can get it to run at over 50MHz for 50/(3*26) =
>> ~640Kk/sec
>>
>> you aren't going to get really high key rates without either lots of
>> silicon or lots of clocks
>
>Maybe I'm not understanding this right, but if the algorithm is fully 
>unrolled, that is to say
>fully pipelined, wouldn't you get one answer out with each clock? So even a 
>lowely 25Mhz FPGA
>would be cranking out 25MKeys/sec.   Even if two $50 parts were needed, that 
>would make a $150
>box that did 25Mkeys/sec, or $6/Mkey/sec, still a great deal!
>
You are all talking about the algorithm, and I looked it up in the net, but
noone could really tell me how it is working. Perhaps someone could tell us
so we can understand how and why u can't get one answer with each clock
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