[HARDWARE] Just Courious......

stoney at sequent.com stoney at sequent.com
Mon Sep 20 13:35:40 EDT 1999


Bravo, finally someone who is NOT talking trash.

On Sat, 18 Sep 1999, taniwha wrote:

> Ha! - I finally solved my mail problems (forgot which email address I
> originally subscribed to the list with). I did a paper design  of
> a cracking chip last year - you can find it at:
> 
> 	http://www.taniwha.com/~paul/rc5.html
> 
> along with verilog source. In silicon it will do ~2.5MKeys/sec
> 200MHz clock in a proto 0.15u library - it's ~50K gates 
> from a naive synthesis run - in practice it's mostly memory
> and datapath (adders and shifters) and would benefit greatly from
> some real datapath design - it could easily end up running at 
> 500MHz and be 1/2 the size - so you might get 6MKeys/sec
> out of it - however I designed it for FPGA implementation (it
> has a larger number of pipe stages because flops are cheap in
> FPGA clbs) I'd guess you could get it to run at maybe 50MHz
> in an FPGA (it takes 3x26 clocks to do a key so that would
> give you about 640Kkeys/sec/chip).
> 
> I have some experience running open-source hardware projects,
> where you build it yourself, and I had had this in mind
> when I was investigating this - the big problem with these designs 
> is that the FPGAs have way too many pins making them unsolderable
> by mear mortals (and hence any kit unbuildable).
> 
> My design hooked to a PC parallel port and multiple chips
> could be assembled into a tree structure to build arbitrary 
> sized cracking engines - check out the article on how to win 
> the rc5 contest in 7 days :-)
> 
> 	Paul Campbell
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> 

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