[Hardware] The market of ASICs (One GigaKey / Second?)

jbass at dmsd.com jbass at dmsd.com
Sun Aug 8 04:33:08 EDT 2004


"Dan Oetting" <dan_oetting at uswest.net> wrote:
> > Hmm ... I'd like to see a rough prototype algorithm for that design.
> 
> The overall block diagram looks much like the parallel version. The
> details for each iteration stage will look considerably different. The
> adders are just a handful of gates and implement carry as a 1 bit time
> delay feeding back into the adder. Rotates require a 32 bit time delay
> and up to 64 bits of storage and 10 selector gates for the variable
> rotate. To compensate for the rotate delays all the other terms carried
> through the stage also need to be delayed. Each stage will contain
> about 320 bits of fifo.

Thanks Dan ... does someone already have a good start on this in VHDL
or Veriog?

John


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