[Hardware] The market of ASICs (One GigaKey / Second?)

[Elektron]

On 10 Aug, 2004, at 04:08, jbass at dmsd.com wrote:

> rotates take a few cycles, but are very possible, so having the FP
> side process the first few stages of round 1 can clearly be useful
> to remove the cycles from the integer pipelines. Consider:

You can multiply and divide to simulate a rotate, but I'm not sure how 
you zero the extra bits. At best, you might be able to save a few 
registers this way, but it's rare that something would work if only 
there was one more register available.

"Removing instructions from the integer pipeline" isn't a big deal on a 
PowerPC, since the number of simple integer units is generally equal to 
the number of (non-branch) instructions you can dispatch per clock 
cycle. I think only multiplication and division takes more than a clock 
cycle to complete, so most of the things can't really be called 
'pipelines'.

The AltiVec cores are more interesting, but completely over my head (so 
are the integer calculations which somehow go with it). I'm not sure 
why you can't do 5 keys at a time either (since if everything's a 
vector, you can do some scalar things too).

It's probably faster to do things at runtime than to code lots of 
constants into the code too (since a 32bit load takes 2 instructions, 
and a floating point load must be done using memory access).

- Purr