[Hardware] The market of ASICs (One GigaKey / Second?)
dan_oetting at uswest.net
Mon Aug 9 21:16:18 EDT 2004
On Aug 9, 2004, at 1:03 PM, Elektron wrote:
> I'm a cycle counter on a good day. 16 cycles per byte of CRC.
> Actually, it was 16 or 17, depending on how the instructions were
> aligned (adding nops to the end could bring it down to 16, but the
> branch target wasn't a multiple of 16). Perhaps the lag caused by the
> misalignment helped.
Why so slow! I get 16 bytes in 17 cycles on a G4. I was all excited
until I found out that IBM apparently already had a patent on the
method and it couldn't actually run that fast because it is limited by
the memory bandwidth.
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