[Hardware] The market of ASICs (One GigaKey / Second?)

jbass at dmsd.com jbass at dmsd.com
Tue Aug 10 05:12:40 EDT 2004


ops ... make that:

	Serial solution would then be (52 + 38 + 15) = 105 LUTs per RC5 engine.
	In addition the design would have to be wrapped with a controlling
	state machine and initialization storage per FPGA.

	Each engine would check a solution every 1248 clocks. An XC2VP70 contains
	just over 65K LUTS, should hold about 628 RC5 engines to check a solution
	roughly every clock at a speed of over 150mhz. Or roughly 75.5MKeys/sec.

	Currently d.net is solving 114,719 GKeys/sec. So it would take 1500 or so
	XC2VP70 FPGAs to match d.net's current performance.

	I have 33M LUT's going into my design, which should net about 314K engines,
	at an average speed of about 120mhz, for about 30,219,445,605 Keys/sec
	after burning about 17.5KW per hour.  $750/mo if I let it run very long,
	which is highly unlikely, as the ROI is nearly zero.


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