[Hardware] Notes... The case for an open client

jbass at dmsd.com jbass at dmsd.com
Mon Aug 16 22:00:56 EDT 2004

"Dan Oetting" <dan_oetting at uswest.net>
> The rotates unfortunately require many more LUTS and have at least a 32 
> clock latency.

For Xilinx Virtex devices, a 3 bit serial adder requires 2 LUT's, and the
associated carry logic and registers. With care (and some luck) you can
build one of the two adders from the carry logic not used by shift registers,
but that is dependent on the FPGA.

The ROTL3 function also requires 2 LUTs (dual 16 bit shift registers) and a
mux which is part of the support logic in a CLB. There is a 29 clock latency,

The ROTL is a bit more complex, and on Virtex Pro devices requires 2 LUT's
(dual 16 bit shifters) plus 5 registers and two muxes, which generally can
be taken from other support logic on the S box chain, and an inverter from
the BY input from some LUT. Virtex Pro LUT's have a shift-out port, that
prior Xilinx FPGAs do not have, which saves considerable logic for this
function. On other FPGA's, it requires either more control logic and mux'es,
or an additional shift register LUT. In just about all cases, there is at
least (32-n) clocks additional latency, and some easy implementations will
always have 32 clocks latency.


More information about the Hardware mailing list