[Hardware] The market of ASICs (One GigaKey / Second?)

[Jim C. Nasby]

A half-million bits of register space doesn't seem that much for a large
FPGA, but I've been out of the EE business for almost 10 years now... :)

Can stages be combined? If they could it should cut down on the number
of registers.

On Tue, Jul 13, 2004 at 11:33:53PM +0200, Michael Meeuwisse wrote:
> Every stage has a different key, thus a different expanded keytable (832 
> bits). Since we have about 600 stages (449200 bits, or 62KiB), it sounds to 
> me we're going to need a lot of internal registers. Even that much that I 
> started looking at external memory (not the entire keytable is needed every 
> stage). And ASICs.
> 
> Hope that answers your question. - wacco
> 
> >If you're pipelining, why do you need memory for any of the intermediate
> >stuff?
> >--
> >Jim C. Nasby, Database Consultant                  jim at nasby.net
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-- 
Jim C. Nasby, Database Consultant                  jim at nasby.net
Member: Triangle Fraternity, Sports Car Club of America
Give your computer some brain candy! www.distributed.net Team #1828

Windows: "Where do you want to go today?"
Linux: "Where do you want to go tomorrow?"
FreeBSD: "Are you guys coming, or what?"