[Hardware] The market of ASICs (One GigaKey / Second?)

[jbass at dmsd.com]

"Jim C. Nasby" <decibel at distributed.net> writes:
> A half-million bits of register space doesn't seem that much for a large
> FPGA, but I've been out of the EE business for almost 10 years now... :)

There is a register per LUT, and very big FPGA's have around 20-50K
luts/registers. So 500K LUT's would require a few chips cascaded for
a solution.

> Can stages be combined? If they could it should cut down on the number
> of registers.

That is in fact part of the general solution to stuffing this into
FPGAs. Fatten all terms which do not need to be registered, into
deep combinatorial logic (skip the register), the terms that are
really memory (register files) so stuff them into LUT's as small RAMs,
and fold the pipeline around the LUT RAM array. Still takes about the
same number of clock cycles to loop the pipeline, but it's a much
smaller structure that can probably be duplicated several times in
a very large FPGA.

John

> On Tue, Jul 13, 2004 at 11:33:53PM +0200, Michael Meeuwisse wrote:
> > Every stage has a different key, thus a different expanded keytable (832 
> > bits). Since we have about 600 stages (449200 bits, or 62KiB), it sounds to 
> > me we're going to need a lot of internal registers. Even that much that I 
> > started looking at external memory (not the entire keytable is needed every 
> > stage). And ASICs.
> > 
> > Hope that answers your question. - wacco
> > 
> > >If you're pipelining, why do you need memory for any of the intermediate
> > >stuff?
> > >--
> > >Jim C. Nasby, Database Consultant                  jim at nasby.net
> > >Member: Triangle Fraternity, Sports Car Club of America
> > >Give your computer some brain candy! www.distributed.net Team #1828