[Hardware] Status on FPGA PCB

Kris Amy kris at amy.id.au
Mon Dec 4 18:47:19 EST 2006


Good work John,

Does that mean you will be running 8 FPGA's @ 240mkeys/sec ?

Also what was the cost to build this?

Cheers,
Kris

-----Original Message-----
From: John L. Bass [mailto:jbass at dmsd.com] 
Sent: Tuesday, 5 December 2006 2:45 AM
To: hardware at lists.distributed.net
Subject: [Hardware] Status on FPGA PCB

Hi Guys,

The FPGA board is nearing completion with a few minor wrinkles. Will not go
out
for fab this morning, but probably in a day or two. Board layout is
frequently
a 90-10 problem, where 90% of the work is getting the last 10% of the
connections
wired ... especially on high density boards like this one.

Wrinkles so far are relatively minor. To get PCI compatability for Spartan-3
parts
requires running the PCI FPGA IO pin banks at 3.0V to keep overshoot inside
PCI specs.
Not a biggie, but requires an additional supply rail. While the chip core is
1.2V,
it's dedicated configuration pins are powered from VAUX at 2.5V, requiring a
little
care when being interfaced with 3.3V IOs.

I could not find the open source compact flash configuration PLD I had seen
last
year. All that is in opencores is one for SD/MMC cards, which unfortunately
isn't
exactly open the last time I looked, as they require licensing for that
interface
from what I understand. I may punt for this proto and just use a Xilinx
config
part to boot up the PCI FPGA and avoid the PLD compact flash development in
the
short run.

Currently I have all 8 fpga's JTAG ports looped off the first fpga, and
intend to
use a little trick I used on another proto -- which is to include a PCI
printer
port in the PCI interface which emulates a Xilinx parallel-III JTAG
interface, as
well as a bi-directional 8bit printer port interface to the fpga
application.
That avoids having to write host operating system drivers in the short term.

I ended up rotating all the parts to place the 8 bit configuration bus along
the
same routing channel.

While most of the IO's are currently wired to the PCI 3.3V power rail, it's
looking
like long term they should be wired to the 1.2V core or 2.5V AUX rail to
avoid
limitations in the number of concurrent switching pins per bank.

Well ... so much for insights from my first Spartan-3 design. Anybody else
done
a design with these parts that can offer any other advice from their
experience?

We are going to need a d.net host application to handle getting keys,
stuffing
them into the FPGA card, and return results to d.net. Any volunteers?

Have fun,
John
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