[Hardware] Fully unrolled RC5 on FPGA

[Martin Klingensmith]

Congratulations.
Any plans for actual implementation or is that too expensive?
--
Martin K

gmeurice at dice.ucl.ac.be wrote:
> Hello,
>
> Here it is:
>
> Results for a Xilinx Virtex4 LX (XC4VLX40-10ff668)
> Fully unrolled architecture
>
> 1) without bRAMs for L shift registers:
> 17427 slices (95%); 26 bRams (27%); 4.33ns (= 230 Mhz)
>
> 2) with bRAMs for the L shift registers:
> 16115 slices (87%); 63 bRAMs (66%); 4.5ns (= 220 Mhz)
>
> It was achieved using Xilinx ISE 8.1, with high effort on both Map and
> Place&Route. (Fortunately) No hand placement was used.
>
> I plan to release the sources on opencores.org
>
>