[Hardware] Fully unrolled RC5 on FPGA

[John L. Bass]

Probably the biggest reason for going ahead and making a DNet FPGA client
is exactly this reason:

[17.2 GHz of CPU's]
[ 976 GB  Storage ]
[ 93" of display  ]
[$100/mo  in power]

as a 200+MKey/sec FPGA should only munch about 24 watts and cost $1.75/mo
to run. At that rate they pay for themselves in a a few months of excess
electricity (saving the planet, if we can get the dino processors turned
off or at least idled).

Much of the processing power in an FPGA is lost in poor routing from the
experiments I did two years ago. A hand/macro tiled design is both faster
and lower power, providing a double win for the effort.

The new V5 FPGA's are lower power, and faster. They have a LUT architecture
that is probably denser for this application. I might take some time next
week to hand layout a stage in the FPGA editor for a V5 CLB block for a
better feel of the density improvements that can be had with the new
architecture.

DNet is only about 0.34% done, with an FPGA project two years ago this would
have already been between 3-5%, and a lot less fuel burned to heat the
planet with dino computers.

John