[Hardware] Fully unrolled RC5 on FPGA

[gmeurice at dice.ucl.ac.be]

Hello,

My design should be modified accordingly:
currently I have a simple incremental 32-bit counter going from 1 to 0
for the LSB of the key.
The MSB are set by the user through an interface.

(I still have to install a CVS client to submit the files)

-- 
Guerric

Sunday, November 19, 2006, 2:09:46 PM, you wrote:

JLB> To have a usable FPGA RC5 core, we also need to make the input counter
JLB> use the same sequence as the DNet clients.  Also we need to generate
JLB> some self check information.

JLB> Anybody know/remember what the specifications for these are?