[Hardware] partially unrolled?

[Martin Klingensmith]

John,
With my incomplete core IIRC I was unable to get it to fit on any
Spartan 3 device. Can something be hand-optimized to be significantly
smaller?
Also, I was unable to find a place that had the XC3S2000 in stock.
Direct from Xilinx?
--
Martin K


John L. Bass wrote:
> ABC> I read on this list that a fully unrolled design is too large for any
> ABC> FPGAs we can afford, while a fully iterated is probably too slow to be
> ABC> useful.
>
> Hi Guys,
>
> I did some poking around at Xilinx FPGA pricing for devices big enough to
> handle a fully unrolled pipelined design, and found that Spartan-3 devices
> are pretty affordable and have enough features to realistically support a
> standard Dnet design.
>
> XC3S2000 devices are just under $100/each, which means it would be practical
> to design a very low end PCI card that supported up to 8 of these devices.
>
> With some pruning, I suspect that we might also be able to fit the core into
> an XC3S1500 device which are price about $75/each in hundreds.
>
> The XC3S1500 device has the added benefit that it's supported by the free
> web pack tools, meaning that hobbiests would not have to invest in the
> $2K Xilinx ISE tools to use their accelerator board.
>
> I suspect the performance will be near that of the Virtex-4 devices, and
> much better on a MegaKey/Sec per Dollar scale.
>
> Guerric should have better numbers in a day or two, and we are collaborating
> on improvements and strategies, off list.
>
> Both of these devices would make practical general purpose FPGA computing
> engines using available C compilers, as well as traditional VHDL/Verilog
> designs. Using low overhead production, boards priced between $150 for a
> single FPGA and about a grand fully loaded are very possible. If done
> commercially, they would have to carry a 2x or 3x markup to cover other
> costs.
>
> The parts are only available in fine pitched BGA, which will increase board
> costs slightly due to the small vias required and extra tight layer to layer
> layup error management. There is a lead-free program for the parts, so we
> can be environmentally friendly too.
>
> ----------
>
> Can someone post what the Dnet core counting sequence, work assignments,
> and work checking requirements are for a valid DNet core to participate?
>
> I'd like to work with Guerric to get a functional first pass core running
> on silicon just to validate the design and do some power/thermal testing.
>
> Have Fun,
> John
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