[Hardware] RC5 with FPGAs

[Dan Oetting]

On Sep 6, 2006, at 12:07 PM, david fleischer wrote:

> By the way, I'm not sure pipelining will bring you
> great benefits in an FPGA. A back of the laptop
> calculation tells me that you'll need approximately
> 1Kbit of memory per key. This may mean that most of
> the archirecture will be shoveling data back and forth
> to the core.

You don't have to store the data. You can recompute it. Instead of 3  
rounds with intermediate data stored between rounds you implement 6  
rounds in a pyramid so the correct data is provided to each stage as  
it's needed..

> I also have a question, can someone help me figure out
> the code in the source ANSI cores? I cannot understand
> how the key increment is done. (that is to say, I see
> what the code is doing, but I cannot figure out why
> this does any good.)

What the code is doing is incrementing the key in byte reversed  
order. Why this is done is because the calculations in the first 2  
1/2 iterations of the first round then become constants so the loop  
can run a few keys per second faster. It won't help your hardware  
unless your design is fully pipelined so you can consolidate the  
first few sets of gates in each pipe. But you still need to implement  
the byte reversed increment to be compatible with the d.net project.