[Hardware] RC5 on FPGA, updated results
martin at nnytech.net
Wed Feb 21 23:41:03 EST 2007
I have written C code that outputs Verilog for most all parameters of
RC5. I have tested it for 40 bit and 72 bit and it works fine.
I'm working on this for my thesis.
Bryan Young wrote:
> It has been a few months without any mention of the hardware
> project. I was wondering about its current status?
> I am currently building up a server box and would like to make sure
> that I have a compatible slot available for the board design, as I plan
> on purchasing a board when they are available. Have you settled on the
> bus interface requirements of the board? PCI, 32 or 64 bit, PCIX, 3.3V
> or 5V, etc.
> Looking forward to hearing from you on status.
> Bryan Young
> Olivier Meyer wrote:
>> Thank you for an amazing Christmas present!
>> On 12/22/06, gmeurice at dice.ucl.ac.be <gmeurice at dice.ucl.ac.be> wrote:
>>> Happy Christmas to everyone.
>>> Some results without placement constraints:
>>> 230 Mkeys/sec on a Virtex4 LX40-10
>>> for 1000 compo: around 200 USD (2007/2008 Resale Price)
>>> for 1 compo: around 400 USD (avnet prices)
>>> 140 Mkeys/sec on a Spartan3 2000-4
>>> for 1000 compo: around 80 USD (2007/2008 Resale Price)
>>> for 1 compo: around 120 USD (avnet prices)
>>> I have some troubles for the use of ISE tools for the Place and Route
>>> step of the constrained Spartan3 design.
>>> John is helping me fixing that.
>>> See you'
>>> Hardware mailing list
>>> Hardware at lists.distributed.net
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