[rc5] Re: Supercomputers & Bovine, Q&A
msissom at dnaent.com
Tue Aug 5 13:03:49 EDT 1997
At 08:57 AM 8/5/97 -0700, you wrote:
>On Mon, 4 Aug 1997, Murray Stokely wrote:
>> I always thought PPC chips were hybid as opposed to true RISC like
>> SPARCS and Alphas. Can anyone with more PPC knowledge shed some light
>> on this for me?
>Nope. PPC chips are pure RISC. Always have been.
Ha! Now things get interesting. Define pure RISC.
Is it memory access limited to register load-store operations?
The PPC abides by this - almost. The single precision FP
load/store instructions don't just load or store. They load
and convert or convert and store. So here's a CISC instruction
that's built into a "pure" RISC proc.
Is it all single cycle instruction execution?
The PPC does not stick to this(lsw)
Is it fixed instruction-opcode mapping?
Nah, refences to r0 often produce the result "0" rather than the
contents of r0(lhzx).
Is it large register arrays?
yep, relatively large anyway.
Or is it just a Reduced instruction set? Reduced relative to what?
The Alpha instruction set is even more reduced than the PPC. Is it
a "purer" RISC?
Marc Sissom | Design Engineer
DNA Enterprises, Inc. | Phone: 972/644-3301
269 W. Renner Parkway | Fax: 972/644-6338
Richardson, Texas 75080 | http://www.dnaent.com
To unsubscribe, send email to majordomo at llamas.net with 'unsubscribe rc5' in the body.
More information about the rc5