[rc5] Re: Supercomputers & Bovine, Q&A

Jeff Leigh robocop at u.washington.edu
Tue Aug 5 11:40:55 EDT 1997


On Tue, 5 Aug 1997, Marc Sissom wrote:
> 
> Is it all single cycle instruction execution?
>  The PPC does not stick to this(lsw)
> 
> Is it fixed instruction-opcode mapping?
>  Nah, refences to r0 often produce the result "0" rather than the
>  contents of r0(lhzx).
> 
> Is it large register arrays?
>  yep, relatively large anyway.
> 

Since when have any of these had anything to do with RISC. What exactly do
you mean by single cycle instruction execution?!? If you mean taking one
clock cycle to finish an instruction, most RISC machines don't do this
anyway. It isn't very efficient. Most RISC chips are pipelined and break
the instructions up into smaller operations.

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