[rc5] RISC sppedups

Michael Graff explorer at flame.org
Sat Jul 19 03:36:48 EDT 1997

Joshua Weage <weage at mtu.edu> writes:

> 	I didn't say I was expecting the key rates to be the same
> as DES, just mentioning the VERY large difference between the
> two.  However, some time ago, I thought it was estimated that it
> only took
> about twice as much time for an rc5 key compared to DES, current
> rates are 10 times slower than DES. (220K/sec rc5, 2M/sec DES
> per processor)  That 220K/sec rate isn't even the standard
> bovine client, the standard v2.002 clients only get 160K/sec.

10 times slower is pretty good, really.  All those rotate instructions
really add up and really hurt on processors which don't implement them
in hardware.

> 	I still think that there can be a substantial improvement
> especially on the 64 bit systems like Sun Ultra's.

The biggest problem is that, unlike DES, RC5 isn't well suited for a
bitslice method, mostly because RC5 uses adds, which don't map to a
bitslice method very well.

Another problem is that even on 64 bit platforms it is difficult to see
a noticable speedup by trying to do two keys at once (one in each half
of the 64-bit registers) because you can't easily treat the one 64-bit
register as two seperate ones and rotate each half independantly.

I've heard the Digital us planning on adding some sort of MMX-like
functions to future Alphas, only they'll be doing it right -- adding
instructions to do it.  If that is the case, they will be adding a
hardware 64-bit rotate as well as a 2*32 bit rotate.  If they do this
soon (and hardware comes out for that processor) the alpha might very
well be the CPU of choice for RC5, especially considering that it could
possibly quad issue and two keys at once.  That's a little under 6.5
keys per loop if my math doesn't suck too much.

> 	Comparing x86 architecture, rc5 is about 4 times slower
> which isn't as bad (and yes I know x86 is better suited for
> rc5 than sparcs.

If only the sparc had a rotate instruction...

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