[rc5] Risc speedup?
rguyom at mail.dotcom.fr
Sat Jul 19 13:39:30 EDT 1997
Michael Graff wrote:
> Remi Guyomarch <rguyom at mail.dotcom.fr> writes:
> > If anybody could do the same for other RISC chips (Alphas, Mips,
> > PowerPC, HP-PA etc...) it will helps a lot.
> It turns out that the other chips (other than Alpha) don't use the
> shifting macros that you improved, so other than the Alpha which
> I have not yet checked with the listed CPUs aren't gonna get a lot
> faster without tweaking.
> Also, it's not clear that hand-written assembly is the answer in many
I've not improved shifting macros. I've not written assembly functions
for anything but x86.
For superscalar machines, it's obvious that checking two keys at once in
the same function and interleaving the code for each key will improve
speed, since much of the RC5 algorithm is serialized.
But in each familly of RISC architectures, there is one-way chips and
two-way or better chips.
For example, UltraSparc has 2 integer units and 1 load/store unit. So it
can do 2 integer operations and a load/store to/from memory each cycle.
But the MicroSparc (cypress in gcc verbiage) is a one-way chip.
Same for PowerPC : 601 is one-way but 603, 604 & 620 are two or three
We already have an ansi-c version of the crunching routine that do one
key at a time, for one-way chips. It will be a bit faster than the
two-keys version on one-way chips, since it will have more registers to
store intermediate results.
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