[rc5] MIPS

Michael Bruck micha at tecnet.de
Fri Jun 13 23:28:48 EDT 1997

Donald J. Rude wrote:
> Speaking of MIPS and slow RC5 on sparcs...
> the SGI port isn't all that fast either.  I would
> guess that it's because of the MIPS architecture
> lacking that nifty ROTL (Rotate Left) command.
> Tho I spose there is no nice way to get around it.
Speaking of intels ROL please remember that this
instruction takes 4 cycles and it blocks both 
pipelines of the processor. The ROL emulation on
other architectures probably uses SHL, SUB, 
SHR, OR. These are 4 instructions. This 
makes 2 cycles for a dual-pipeline 2 instr/cycle
processor. Of course this is a simplified calculation.
(The ROTL3 takes 2 cycles on intel. For the emulation you
need SHR, SHL, OR = 1.5 cycle.)

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