[rc5] MIPS

Michael Bruck micha at tecnet.de
Fri Jun 13 23:39:12 EDT 1997

Michael Bruck wrote:
> processor. Of course this is a simplified calculation.
> (The ROTL3 takes 2 cycles on intel. For the emulation you
> need SHR, SHL, OR = 1.5 cycle.)
I must correct myself ROL reg,imm takes 1 cycle on pentiums.
But again it blocks both pipelines.

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