[rc5] MIPS

Chris Maxwell maxwell at bluenose.hfx.prior.ca
Mon Jun 16 13:34:36 EDT 1997


  WRT RISC processors being slow:

  A friend of mine has a SPARC assembler book, but I can't 
see how to make it go faster.  If one can guarantee 
there will be no request for a shift > WORDSIZE, 
then we can save two instructions per ROTL (those ANDs), 
which would help.  However, I did not get an opportunity to 
check for whether they were there just for correctness, 
or because they were required.  We could 
remove one of them by only doing the AND at the 
ROTL macro, not both the SHR and SHL macros.
Certainly the ROTL3 macro can be stripped down,
it will never be > RC5_ROTMASK.
  

Thoughts anyone?

  Also, if anyone wants to take a crack at it, 
I can try typing in SPARC instructions 
a bit at a time, or they can direct me to start 
with only the SHIFT, OR/AND, and BRANCH sets, or 
such.  The way it is done now is as efficient as
I can think of, but I am not an assembly programmer.


  For those who can not find the code (I am not entirely 
certain where the person I got it from got it), the 
client.h file goes something like this:


#define RC5_WORDSIZE 32
#define RC5_ROTMASK  (RC5_WORDSIZE - 1)


#define SHL(x, s) ((RC5_WORD) ((x) << ((s) & RC5_ROTMASK)))
#define SHR(x, s) ((RC5_WORD) ((x) >> ((RC5_WORDSIZE) - ((s) &
      RC5_ROTMASK))))

#if defined (SPARC) || defined (MIPS) || etc
# define ROTL(x, s) ((RC5_WORD) (SHL((x), (s)) | SHR((x), (s))))
# define ROTL3(x) ROTL(x, 3)
#endif


GCC almost exactly turns this into the same assembly instructions, 
(other than miscellaneous LOAD/STORE and such.)


"Donald J. Rude" said something like,
> Speaking of MIPS and slow RC5 on sparcs...
> the SGI port isn't all that fast either.  I would
> guess that it's because of the MIPS architecture
> lacking that nifty ROTL (Rotate Left) command.
> 
 
Chris Maxwell,  PRIOR Data Sciences
Chris.Maxwell at prior.ca    (902) 423-1333 ext 253
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