[RC5] Use of FPU on Intel 486 and P5 processors
b.ford at qut.edu.au
Tue Jan 6 10:48:42 EST 1998
There has been some comment on the possibility of using the floating
point unit (FPU) on Intel processors in parallel with the integer
unit to help process more keys.
I have tested this idea on a 486 and a P5 and found that instructions
to the FPU stall the integer pipeline for the duration of the FPU
It may be different on other chips, or even later Intel chips, but I
don't have access to those. If after testing you discover that the
FPU does execute in parallel without stalling the integer pipeline, I
have available a 34 step FPU sequence that will do one cycle of
round 1 of the key expansion. Foolishly, though partly as an
intellectual exercise, I developed this before testing the
As MMX instructions use the FPU registers I suspect that they too
will stall the integer pipeline but this should really be tested.
Just to add some facts to this discussion.
Bruce Ford b.ford at qut.edu.au
Teaching and Learning Support Services Ph: +61 7 3864 3383
Queensland University of Technology
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