[RC5] Use of FPU on Intel 486 and P5 processors

Remi Guyomarch rguyom at mail.dotcom.fr
Mon Jan 12 23:31:52 EST 1998


The Pentium suffer from the same problem : it can only decode 2
instructions per cycle, so the FPU unit can't be used in conjonction
with standard integer pipelines. Same thing for the AMD K6.
PentiumPro / PII *can* decode 3 instructions per cycle, so there is
something to do here.

Mary Conner wrote:
> 
> I had a look at the feasibility of using the FPU to do keys in parallel
> with with regular integer pipelines on x86 processors, looking specially
> at the Cyrix 6x86, since that is the processor I have.  The biggest
> problem that I could see is that the FPU instructions still have to go
> through the integer pipelines for decoding, and the instruction prefetch
> unit is capable of delivering two instructions per cycle, one to each
> pipeline, and FPU instructions can only go to the X pipeline.
[...]

-- 
RÈmi		Don't waste your computer's time. Distribute it!
			http://www.distributed.net/
	    RC5 cores source code : http://wwwperso.hol.fr/~guyom001/

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