[RC5] Use of FPU on Intel 486 and P5 processors

gindrup at okway.okstate.edu gindrup at okway.okstate.edu
Tue Jan 13 08:48:56 EST 1998


        The FPU and V-pipe are coincident.  Certainly one can't issue two 
     integer instructions and a FPU instruction on the Pentium, but a 
     pairable FPU instruction can be issued one decode cycle later than a 
     pairable integer instruction.  Further, once the FP instruction 
enters 
     its concurrent stage (at the end) another (potentially pair of) 
     integer instruction can be decoded and queued to both pipes.
        The PPro's FPU is off of port0 as is one of its integer units.  
     Port1 handles the other parallel integer unit.  So on the PPro, use 
of 
     an FPU instruction preempts integer unit pairing for one cycle until 
     the FPU instruction is passed of to the microcoded executor.
        The the PII and PPro can *retire* up to three instructions per 
core 
     cycle has nothing to do with their issue parallelizability.  For 
     example, the PPro can *issue* up to five instructions per core cycle 
     (assuming that the instructions are wildly orthogonal and all decode 
     to short ucode sequences).  The Pentium can issue wto instructions 
per 
     core cycle.  Issues through the U-pipe are basically integer, state, 
     and flow-control statements.  Issues through the V-pipe are 
basically 
     integer, FPU, or MMX.  MMX P5s relax several of the pairing 
     restrictions, but regardless, a P5 can either issue a pairable FPU 
     instruction, a pairable MMX instruction, or a pairable integer 
     instruction through the V-pipe (assuming the U-pipe contains a 
     pairable instruction).
        (Oddly, the FPU stack exchange instruction is pairable with many 
     different FPU instructions indicating that they can be issued on 
     successive core clocks as long as they don't have register 
     dependencies.  Intel suggested using thie property of the 486 and P5 
     as ways of increasing parallelization through the FPU.  Of course, 
     careful register tracking is required.)
            -- Eric Gindrup ! gindrup at Okway.okstate.edu


______________________________ Reply Separator 
_________________________________
Subject: Re: [RC5] Use of FPU on Intel 486 and P5 processors 
Author:  <rc5 at llamas.net > at SMTP
Date:    1/12/98 11:31 PM


The Pentium suffer from the same problem : it can only decode 2 
instructions per cycle, so the FPU unit can't be used in conjonction 
with standard integer pipelines. Same thing for the AMD K6. 
PentiumPro / PII *can* decode 3 instructions per cycle, so there is 
something to do here.
     [snip]
-- 
REmi                Don't waste your computer's time. Distribute it!
     [snip]


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