[RC5] Re: rc5-digest V1 #249

Brice D. Fleckenstein ciga at surf-ici.com
Sat Jan 2 14:37:33 EST 1999


> The intel x86 chips have a hardware-single-cycle-rotate
> instruction. That is, bits can be rotated around in the
> registers by any arbitrary number. The RC5 algorithm
> depends very heavily on this kind of bit manipulating
> operation. Most processors do not support this.

 More accurately, the Pentium-Pro, Celeron, and PII Intel CPUs have this
support in hardware.

 I believe it's also supported in hardware by various PowerPC CPUs, but
I don't know for sure.

 The AMD K5 specifically DOES have this, which is why my K5-PR166
machines  that run at 117.5 Mhz are FASTER than Intel PentiumMMX
machines running at 166 Mhz, even after the MMX RC5 core was added to
the clients.

 Intel CPUs prior to the Pentium Pro, specifically including any Intel
Socket 7 chip, do NOT support this instruction in hardware.

 The AMD K6 apparently had to drop that instruction from hardware in
order to make space to add the MMX instruction set - K6's are quie a bit
slower

 The IBM/Cyrix and IDT WinChip C6 CPUs do not support that instruction
in hardware.

-- 

 Reply-to has been de-spammed. Real email address below.

 Brice D. Fleckenstein
 EMail: bricef at indy dot net

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