[RC5] K6-2/350 vs PII 266 mobile performance - oops!
cberry at acorn.com
Mon Jan 4 13:18:08 EST 1999
Marc Sissom wrote:
> So there is a minimum 5 instruction penalty for procs
> that don't support a native arbitrary rotate, 2 SHIFTs,
> 2 ANDs and an OR. Sometimes a multi-bit shift is not
> supported in a single cycle so the cost is even greater...
Provided the shift produced 0s in the "empty" bits (which
is (afaik) always the case with a left shift, and is also
the case with a logical (as opposed to arithmetic) right
shifts) you don't need the ANDs.
So on the majority of processors, you're looking at 2 shifts
and an OR, assuming a multi-bit shift is available.
To unsubscribe, send 'unsubscribe rc5' to majordomo at lists.distributed.net
rc5-digest subscribers replace rc5 with rc5-digest
More information about the rc5