[RC5] G4 benchmarks

Ryan Malayter rmalayter at bai.org
Fri Oct 29 17:06:08 EDT 1999


Looking at the AltiVec instruction set, it would seem that the instruction vec_rl instruction would allow for something like a threefold increase in speed for the PowerPC client when run on the G4.

AltiVec can, it appears, do all necessary RC5 operations on four 32-bit or two 64-bit unsigned integers simultaneously. Plus, the (already fast) PowerPC integer core can run at the same time! I figure that a threefold key rate improvement would definitely be possible, assuming the code were hand-optimized in assembler.

	-ryan-

>From the AltiVec C/C++ extenstions:
----------------------------------
vec_rl
Vector Rotate Left
(maps to assembler instruction: vrlw d,a,b)

d = vec_rl(a,b)
n ¬ number of elements
do i=0 to n-1
d i ¬ ROTL(a i , b i )
end

Each element of the result is the result of rotating left the corresponding element of a by the number of bits indicated by the corresponding element of b.

-----Original Message-----
From: Dan Oetting [mailto:oetting at gldmutt.cr.usgs.gov]
Sent: Friday, October 29, 1999 11:09 AM
To: rc5 at lists.distributed.net
Subject: Re: [RC5] G4 benchmarks


>-----BEGIN PGP SIGNED MESSAGE-----
>
>On Thu, 28 Oct 1999 13:26:26 -0400, Joe Kazura wrote:
>
>>The code needs to be updated on RC5 to be 128-bit and to use the
>>Altivec instruction set.
>>
>>The current BETA client of RC5 gives about the same for a G4 @ 450Mhz
>>as it does for a G3 @ 450 Mhz.
>>
>
>that sounds nice, except rc5 is a purely 32 bit algorithm, so going 64 or
>128 bits
>does not help ( it uses lots of 32 bit rotates),

It is nice since AltiVec can treat those 128 bits as 4 32 bit operands to
do 32 bit dynamic rotates and 32 bit adds on 4 words at a time.

>and the cores are available at http://www.distributed.net/source/ for
>anyone who
>wants to try and create a Altivec core

-- Dan Oetting <oetting at ghtmail.cr.usgs.gov>


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