[RC5] AMD core

Dan Oetting oetting at gldmutt.cr.usgs.gov
Tue Feb 15 19:27:19 EST 2000

At 16:54 -0700 2/14/2000, Bruce Ford wrote:
>At 03:15 14/02/00 +0100, you wrote:
>>Has anyone looked further into the AMD core optimisation as discussed in:
>>It looked very promissing to me, but I'm afraid I have niether the
>>programming skill, nor the time to look into it. If anyone shoud however
>>know about some good literature about this subject, i would be glad to hear
>>about it.
>I have started some work on theoretical code.  The main changes to the
>original idea is that I have decoupled the round 3 key expansion and
>encryption phases and will attempt to do most of the encryption using MMX
>instructions while the integer code does the key expansion for the next two
>keys.  Originally I had MMX instructions doing part of round 1 of the key
>expansion of the next two keys while the integer code finished it off.

This is essentially what I have done for the AltiVec core. You want to
start out in the integer unit where you can collapse the common expression
for the parallel keys then finish it off in the vector unit.  The easiest
way to start the assembly code for the two instruction streams is to
disassemble the output of a compiler. I used a spreadsheet to align the two
streams for optimum interleaving then a few quick substitutions in an
editor reformatted the columns into the final assembly code.

The other option is to just buy a G4 PowerPC that is already crunching RC5
blocks twice as fast as the "theoretical" limit of the Athlon core at the
same clock speed.

-- Dan Oetting <oetting at ghtmail.cr.usgs.gov>

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