[RC5] Performance on P-IV

David McNett nugget at slacker.com
Thu May 10 10:46:18 EDT 2001


On 10-May-2001, Bjoern Martin wrote:
> The pipeline of the P-IV is pretty long (i think 12 clocks). This
> means, every instruction takes 12 clocks.
> [snip]
> So what do the gurus say, is this guess true? :)

Bruce Ford is probably the closest to the P4 optimizations in the client.
I know that Moose is working with some Intel bit grinders, but I believe
their focus is on an Itanium core, and not P4 optimizations.

According to the info at http://www1.distributed.net/~fordbr/ from Bruce,
the P4 has a 4 clock latency on ROTL ops which are critical to RC5 
performance.  This handicaps the P4 in a similar manner as the K6 
for RC5 performance.  (OGR would be unaffected by this).

On the page above, bruce has posted our current best-case clocks/key for
all the various strata of x86-compatible CPUs.  Hopefully he'll weigh in
on this thread with more info than I can provide.

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