[RC5] Performance on P-IV
frival at zk3.dec.com
Thu May 10 15:42:38 EDT 2001
Uhh...huh? /me thinks you mean IA64 - the P4 is still a 32 bit chip. The
new instructions that it uses are called SSE2, but they are streaming SIMD
instructions that are _new_, not replacements of old common ones.
Stephen Garrison wrote:
> IMHO there is a more important item than the pipeline depth. If I remember
> correctly, the P-IV is entirely hardwired to do 64 bit instructions only.
> Any P-III or earlier used 32 bit instructions. So, anything written for an
> earlier Pentium, ie the dnet code, has to be translated by chip into 64
> bit code. And, this translation process is generally extremely slow.
> Until the dnet people get a chance to rewrite the assembly code in IA-64
> (the new instruction set) instead of x86, the core is going to be
> SSSLLLOOOWWW. Once the code is rewritten to use all of the new features of
> the chip, including the longer pipeline, it should be much faster.
> As for how it will then compare per MHz with an Apple or an AMD machine, I
> have no clue. But I bet it will be much improved at the very least.
> My $0.025 (adjusted for inflation)
> Stephen Garrison
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