[RC5] Performance on P-IV

Enojon enojon at ATTGLOBAL.NET
Sat May 12 16:37:07 EDT 2001


It seems every manufacturer is awaiting the 'fallout' of the other rivals.

For the record, Sun, HP and IBM are vendors with 64-bit chips
[Motorola piggybacks with IBM].   HP migrated its UX boxes from
32-bit to 64-bit a few years ago.  IBM PPC is a "new" 64-bit chip,
and the mainframe tech was at 31-bit and is moving into 64-bit
[just today, I read feedback from application/systems programmers
on 'features' that are cropping up in the underlying systems-ware]

Going up to 64-bit is being addressed with the same caution as
approach of Y2k.   Reading HP's documents on 64-bit migration
is better than a cheap teen-focused horror flick!  [the legend of
the "long long" integer that wasn't signed extended]

===8-O  !!

----- Original Message -----
From: "Ferry van Steen" <td at salesint.com>
To: <rc5 at lists.distributed.net>
Sent: Friday, May 11, 2001 4:13 AM
Subject: Re: [RC5] Performance on P-IV


> It indeed has 32b IA I know that for a fact. The Itanium will be the first
> 64b IA from Intel I believe and is scheduled for release end this year I
> believe. If I'm not mistaken the P-IV's release was originally planned end
> 99 mid 2000 if I'm not mistaken. However there where a lot of problems
with
> the RIMM's, they wouldn't run stable. In fact RIMM's should have been
> released with P-III's already but they didn't get that stable either so
they
> released P-III's with plain SDRAM since they where behind on schedule.
>
> I'm not to sure about the correctness of this info... But I believe it to
> have a 90% trueness :-) (came from reliable source)
>
> regards
>
> ----- Original Message -----
> From: "Peter Rival" <frival at zk3.dec.com>
> To: <rc5 at lists.distributed.net>
> Sent: Thursday, May 10, 2001 8:42 PM
> Subject: Re: [RC5] Performance on P-IV
>
>
> > Uhh...huh?  /me thinks you mean IA64 - the P4 is still a 32 bit chip.
The
> > new instructions that it uses are called SSE2, but they are streaming
SIMD
> > instructions that are _new_, not replacements of old common ones.
> >
> >  - Pete
> >
> > Stephen Garrison wrote:
> >
> > > IMHO there is a more important item than the pipeline depth. If I
> remember
> > > correctly, the P-IV is entirely hardwired to do 64 bit instructions
> only.
> > > Any P-III or earlier used 32 bit instructions. So, anything written
for
> an
> > > earlier Pentium, ie the dnet code, has to be translated by chip into
64
> > > bit code. And, this translation process is generally extremely slow.
> > >
> > > Until the dnet people get a chance to rewrite the assembly code in
IA-64
> > > (the new instruction set) instead of x86, the core is going to be
> > > SSSLLLOOOWWW. Once the code is rewritten to use all of the new
features
> of
> > > the chip, including the longer pipeline, it should be much faster.
> > >
> > > As for how it will then compare per MHz with an Apple or an AMD
machine,
> I
> > > have no clue. But I bet it will be much improved at the very least.
> > >
> > > My $0.025 (adjusted for inflation)
> > >
> > > --
> > > Stephen Garrison
> > >
> > > --
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