[RC5] Performance on P-IV

Ryan Malayter rmalayter at bai.org
Fri May 11 12:58:15 EDT 2001


I believe it's a bit-slicing core, where 32 (or more?) separate keys are
worked on at once in each AltiVec register. One bit of each key being worked
on is mapped to each bit of the register at a time. This is sort of the way
the MMX core works on PII/III machines, but the AltiVec engine is a lot more
capable. It has a lot more registers and ALU circuitry because of the vector
capabilities, and can probably handle 3 or more registers bit slicing at a
time.

But I could be totally wrong.

Dan Oetting, are you out there, buddy?

	-ryan-

-----Original Message-----
From: James Sharp [mailto:jsharp at psychoses.org]
Sent: Thursday, May 10, 2001 4:19 PM
To: 'rc5 at lists.distributed.net'
Subject: RE: [RC5] Performance on P-IV



> The G4 is by far the most efficient processor out there for RC5 right now
in
> terms of keys/clock. This is a result of the AltiVec-optimized code. I'm
not
> close enough to the dnet P4 project to know, but who knows what some great
> coder could make of the P4's updated SIMD architecture?

How exactly does the G4/AltiVec code work?  RC5 isn't truly vectorizable,
because of inter-loop dependencies.  Does the dnet stuff break it down
into parallel tasks using the vector registers each as a separate
pseudo-processor?


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