AW: [RC5] Athlon XP/MP even faster? K5 faster than K6!
MastarPete at att.net
Mon Oct 22 21:21:06 EDT 2001
I realize this probably is probably not perfectly accurate... at least maybe not for the P4..
but I played around with the keyrate calculator that's on that page..
> http://www1.distributed.net/~fordbr/rc5calc.html < (nice job bruce)
and according to that...
a single P4 would have to be running about 3797.86 Mhz in order to come close to
a single Athlon running at 1400 Mhz...
P4- 4964.52 Kkeys/sec
Athlon- 4964.53 Kkeys/sec
they both "get" about..
1597 work units per day (or blocks or 2^28 keys)
49 packets of 2^33 (33*2^28) keys per day
11185 work units per week
I just thought I'd share.. 8^p
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----- Original Message -----
From: "Bruce Ford" <b.ford at qut.edu.au>
To: <rc5 at lists.distributed.net>
Sent: Monday, October 22, 2001 9:23 AM
Subject: Re: AW: [RC5] Athlon XP/MP even faster? K5 faster than K6!
> > I believe this is because the K5 has a more powerful / effective (ie.
> > higher IPC)
> > integer unit than the K6. That was generally the K5's strength over the
> > IIRC the K5 was based on NexGen's work, while the K6 was using the Chomper
> > core.
> The K5 had pairable single clock cycle rotates.
> On the K6 the rotate instruction is a vector decode to RISC86-ops. Guessing
> that the rotate left is simulated with "copy reg-shift left-negate
> mask-shift right-or" makes it take a minimum of 4 clock cycles (with some
> pairing) and shifts are only allowed in alux.
> Tried to improve the K6 core by using the MMX code on the K6-2/K6-3 and
> although it could be made to work for a single "cycle" of the RC5 algorithm,
> it seemed to have extra clocks added when the instruction sequence did not
> align on a 32 byte boundary. This made it near impossible (I stopped trying)
> to extend to the 26 cycles by 3 rounds required.
> FWIW the keys/s/MHz for the x86 cores are available at
> There may be some advantage to mixing MMX code with the integer code for the
> K7 core. Basically this uses spare decode cycles (where we can't find 3
> instructions to run in parallel due to the paucity of registers) to run MMX
> code which does part of the first round of key expansion for the next pair
> of keys while the current pair are being processed by the integer code.
> Bruce Ford
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