[RC5] VIA C3

Enoch enojon at ATTGLOBAL.NET
Mon Sep 3 18:13:37 EDT 2001


at 600mhz, the VIA Cx III performs at 50% of the Intel and AMD equivalent
rated chips.  

It may not be due to ooo exec alone, but VIA C3 lacking equivalent number of
parallel microcode units.  Nevertheless, on microbenching, the core picked the
"SS Ath" for best performance albeit performing at far slower keys/sec rate.

Maybe L2 cache size of the C3?

----- Original Message ----- 
From: "Peter Cordes" <peter at llama.nslug.ns.ca>
To: <rc5 at lists.distributed.net>
Sent: Wednesday, August 29, 2001 7:23 PM
Subject: Re: [RC5] VIA C3


> On Wed, Aug 29, 2001 at 01:02:53AM +0800, Jin-Wei Tioh wrote:
> > Would the lack of out-of-order execution on the VIA C3 processor
> > significantly impact its RC5-64 performance?
> 
>  Probably not.  Out of order execution gives you better performance
> with code that isn't perfectly tuned, and gives you more flexibility
> when tuning.  For something like RC5, it's probably still possible to
> keep all the (applicable) execution units running almost all the time. 
> 
>  Intel's P5 core was a superscalar in-order execution design.  (U pipe
> and V pipe...)  The RC5 core optimized for it kept both pipes full,
> AFAIK.
> 
> > Would any other aspects of its design affect it?
> 
>  How many instructions per clock it can issue (how many pipes there
> are) is important, as well as the latency and throughput of the important
> instructions like rotate, and MMX operations.
> 
> -- 
> #define X(x,y) x##y
> Peter Cordes ;  e-mail: X(peter at llama.nslug. , ns.ca)
> 
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>  my day so wretchedly into small pieces!" -- Plautus, 200 BCE
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