[RC5] VIA C3
enojon at ATTGLOBAL.NET
Thu Sep 6 02:43:52 EDT 2001
----- Original Message -----
From: "Peter Cordes" <peter at llama.nslug.ns.ca>
To: <rc5 at lists.distributed.net>
Sent: Wednesday, September 05, 2001 9:02 PM
Subject: Re: [RC5] VIA C3
> On Mon, Sep 03, 2001 at 05:13:37PM -0400, Enoch wrote:
> > at 600mhz, the VIA Cx III performs at 50% of the Intel and AMD equivalent
> > rated chips.
> > It may not be due to ooo exec alone, but VIA C3 lacking equivalent number of
> > parallel microcode units. Nevertheless, on microbenching, the core picked the
> > "SS Ath" for best performance albeit performing at far slower keys/sec rate.
> How does the keyrate of the best core perform vs. the best core on an
> equal clock speed Intel or AMD? How about vs. an equally priced Intel
> or AMD? (the equal price comparison might make the C3 seem ok (or
> maybe not, I don't know), but if you can't buy it in a fast enough
> speed grade, it's a moot point...)
A 466mhz Celeron turns out about 1.3 M keys/sec @ $40-49.per chip
A 600mhz C3 turns out about 738K keys/sec @ $40-45 per chip
> > Maybe L2 cache size of the C3?
> That wouldn't make any sense. We're talking about RC5. The core
> doesn't touch enough memory to use anything more than the L1 cache,
> and the inner loop fits entirely in registers. Even L1 cache speed
> should have almost no effect on RC5 keyrate. (within reason - turning
> it off in the BIOS setup will have a huge effect, mostly because that
> would turn off the L1 instruction cache as well! Ouch!)
I'll check, but last time I stuck a C3 into the "as is" 466mhz unit
and rated as 1/2 (or 1/3) of Celeron performance with equal cache
settings and speed of memory. [took a DOS floppy booted under
Celeron power, then swapped out chip for C3 and re-booted same
DOS floppy, and Cache L1 and L2 were turned on in the BIOS]
I also used the same "cooling fan" per chip.
A non-cooled 200mhz Power PC chip hits approx 80% of the C3 600mhz
performance--unless I have some bogus chips (MII's masquerading as MIII's)
but the BIOS recognizes them as MIII.
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